With the development of display technology, the flat panel device, such as Liquid Crystal Display (LCD) possesses advantages of high image quality, power saving, thin body and wide application scope. Thus, it has been widely applied in various consumer electrical products, such as mobile phone, television, personal digital assistant, digital camera, notebook, laptop, and becomes the major display device.
Most of the liquid crystal displays on the present market are back light type liquid crystal displays, which comprise a liquid crystal display panel and a back light module. Generally, the liquid crystal display panel comprises a CF (Color Filter) substrate, a TFT (Thin Film Transistor) substrate, a LC (Liquid Crystal) sandwiched between the CF substrate and the TFT substrate and sealant.
Low Temperature Poly Silicon (LTPS) is a kind of liquid crystal display technology which has been widely applied in the small, medium size electronic products. The electron mobility of the traditional amorphous silicon material is about 0.5-1.0 cm2/V·S but the electron mobility of the Low Temperature Poly Silicon can reach up to 30-300 cm2/V·S. Therefore, the Low Temperature Poly Silicon display has many advantages of high resolution, fast response speed and high aperture ratio.
However, on the other hand, the volume of the LTPS semiconductor element is small and the integration is high. The manufacture process of the entire LTPS array substrate is complicated, and the production cost is higher.
As shown in FIGS. 1-6, the manufacture method of CMOS (Complementary Metal Oxide Semiconductor) LTPS array substrate according to prior art comprises steps of:
step 1, as shown in FIG. 1, providing a substrate 100, and defining a NMOS (Negative channel Metal Oxide Semiconductor) region and a PMOS (Positive channel Metal Oxide Semiconductor) region on the substrate 100, and depositing a first metal layer on the substrate 100, and patterning the first metal layer with the photolithographic process to obtain a light shielding layer 200 in the NMOS region;
step 2, as shown in FIG. 2, sequentially depositing a buffer layer 300 and an amorphous silicon layer (a-Si) on the and the substrate 100, and converting the amorphous silicon layer (a-Si) into the polysilicon layer (poly-Si) by an Excimer Laser Annealing process (ELA), and patterning the polysilicon layer with the photolithographic process to obtain a first polysilicon layer 410 in the NMOS region and a second polysilicon layer 420 in the PMOS region;
step 3, as shown in FIG. 3, coating a first photoresist layer 510 on the first polysilicon layer 410, the second polysilicon layer 420 and the buffer layer 300, and after employing a mask to implement exposure, development to the first photoresist layer 510, implementing channel doping to the first polysilicon layer 410 in the NMOS region;
step 4, as shown in FIG. 4, coating a second photoresist layer 520 on the first polysilicon layer 410, the second polysilicon layer 420 and the buffer layer 300, and after employing a mask to implement exposure, development to the second photoresist layer 520, implementing N type heavy doping to two ends of the first polysilicon layer 410 in the NMOS region;
step 5, as shown in FIG. 5, sequentially depositing a gate insulation layer 600 and a second metal layer on the first polysilicon layer 410, the second polysilicon layer 420 and the buffer layer 300, and patterning the second metal layer to obtain a first gate 710 and a second gate 720 correspondingly above the first polysilicon layer 410 and the second polysilicon layer 420, respectively; employing the first gate 710 to implement N type light doping to the first polysilicon layer 410;
step 6, as shown in FIG. 6, coating a third photoresist layer 800 on the first gate 710, the second gate 720 and the gate insulation layer 600, and after employing a mask to implement exposure, development to the third photoresist layer 800, implementing P type heavy doping to two ends of the second polysilicon layer 420;
step 7, sequentially manufacturing structures, such as an interlayer insulation layer, a source-drain layer, a flat layer, a common electrode layer, a passivation layer and a pixel electrode layer on the first gate 710, the second gate 720 and the gate insulation layer 600.
In the aforesaid manufacture method of the LTPS array substrate, all these three processes of the channel doping and N type heavy doping of the first polysilicon layer 410 of the NMOS region, and the P type heavy doping of the second polysilicon layer 420 of the PMOS require the photolithographic process to implement doping, and needs three masks in total. The manufacture process is complicated and the production cost is high. Therefore, there is a need to provide a manufacture method of a LTPS array substrate to solve the technical problem.